1. Field of the Invention
The invention relates to a current-mode identifying circuit, more particularly to a current-mode identifying circuit for multilevel flash memories.
2. Description of the Related Art
In conventional semiconductor memory devices, by pre-charging the floating gate of a memory cell of a EEPROM, desired data can be written into the memory cell. However, the storage density of the conventional EEPROM is not high enough if only one-bit data can be stored per cell. Recently, multilevel flash memories for enhancing the storage density of electrically alterable nonvolatile memories have been proposed so as to store more than one-bit data per cell. For storing n-bit data per cell, a floating gate of a flash cell must be capable of being charged tom (m=2n) levels. Sensing time and sensing result are important design considerations for a multilevel flash memory.
A conventional parallel current-mode multilevel identifying circuit for a multilevel flash memory has been proposed heretofore in an article by C. Calligaro and others, entitled xe2x80x9cHigh-speed Parallel Sensing Scheme for Multilevel Nonvolatile Memoriesxe2x80x9d, Proc. Int. Workshop on Memory Technology, Design and Testing, pp. 96-101, 1997. The circuit includes a conventional current comparator composed of a differential amplifier circuit that may result in a voltage drift during amplifying. A correcting circuit is thus necessary to correct the voltage drift, thereby resulting in a complicated construction such that the conventional multilevel identifying circuit has a larger chip size and higher production costs. Furthermore, due to the use of the differential amplifier circuit, pre-charging is needed, and power consumption is thus increased.
Another conventional parallel current-mode identifying circuit for a multilevel flash memory has been proposed in an article by D. Montanari, J. V. Houdt and G. Groeseneken, entitled xe2x80x9cNovel Level-Identifying Circuit for Flash Multilevel Memoriesxe2x80x9d, IEEE J. of Solid-State Circuits, vol. 33, no. 7, pp. 1090-1095, 1998. The circuit includes a conventional current comparator that utilizes a xe2x80x9cwinner-take-allxe2x80x9d discriminator to identify a current level of a flash cell. Although the conventional current comparator with the discriminator has a simpler construction as compared with one using a differential amplifier circuit, it introduces a delay time equal to about 9 ns, thereby resulting in a relatively slow sensing speed.
Therefore, the object of the present invention is to provide a current-mode identifying circuit for a multilevel flash memory that can enhance data-sensing speed of the flash memory, that has a relatively small size and that can be fabricated at a relatively low cost.
According to the present invention, a current-mode identifying circuit is adapted for use with a multilevel flash memory having a flash cell array that includes a plurality of flash cells. The identifying circuit is adapted to identify a level associated with a cell current flowing through a selected one of the flash cells, and comprises:
a current duplicating circuit having an input adapted to be coupled electrically to the selected one of the flash cells, and a plurality of outputs, the current duplicating circuit duplicating the cell current flowing through the selected one of the flash cells, and outputting a duplicate cell current at each of the outputs;
a plurality of nodes, each of which is coupled electrically to a corresponding one of the outputs of the current duplicating circuit so as to receive the duplicate cell current therefrom;
a plurality of reference current generating units, each of which is coupled electrically to a corresponding one of the nodes and draws a predetermined reference current from the corresponding one of the nodes such that a difference current between the duplicate cell current and the predetermined reference current flows out from the corresponding one of the nodes;
a plurality of current comparators, each of which has an input end coupled electrically to a corresponding one of the nodes for receiving the difference current therefrom, and an output end for outputting a logic signal corresponding to magnitude of the difference current received thereby; and
an encoder coupled electrically to the output ends of the current comparators for receiving the logic signals therefrom, the encoder encoding the logic signals so as to identify the level associated with the cell current flowing through the selected one of the flash cells.